The present invention relates in general to a static random access memory (SRAM), and, more particularly, to an SRAM having improved latch-up characteristics.
RAM chips are well known in the art. An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. A prior art six transistor CMOS SRAM cell 1 is shown schematically in FIG. 1. The SRAM cell 1 includes two n-type access transistors 5, 6, two p-type pull-up transistors 7, 8 acting as load devices, and two n-type pull-down transistors 9, 10, with the pull-transistors 7,8 and pull-down transistors 9, 10 forming two CMOS inverters. The SRAM cell 1 has two states: logic state “0” and logic state “1”. By convention, if logic state “0” is designated by node A having a high voltage and node B having a low voltage, then logic state “1” has the opposite stored voltages, i.e., node A having a low voltage and node B having a high voltage.
In logic state “0” the high voltage on node A turns on the pull-down transistor 9 and turns off the pull-up transistor 7, whereas the low voltage on node B turns off the pull-down transistor 10 and turns on the pull-up transistor 8. Because the pull-down transistor 9 is on and the pull-up transistor 7 is off, current flows through the pull-down transistor 9 to a voltage supply VSS (ground), thereby maintaining a low voltage on node B. Because the pull-up transistor 8 is turned on and the pull-down transistor 10 is turned off, current flows from a voltage supply VCC through the pull-up transistor 8, thereby maintaining a high voltage on node A.
To change the state of the SRAM cell 1 from a logic “0” to a logic “1”, a column line 3 and a column line complement 2 are provided with a low and a high voltage, respectively. Then, the access transistors 5 and 6 are turned on by a high voltage on a row line 4, thereby providing the low voltage on the column line 3 to node A and the high voltage on the column line complement 2 to node B. Accordingly, the pull-down transistor 9 is turned off and the pull-up transistor 7 is turned on by the low voltage on node A and the pull-down transistor 10 is turned on and the pull-up transistor 8 is turned off by the high voltage on node B, thereby switching the state of the circuit from logic “0” to logic “1”. Following the switching of the state of the SRAM cell 1, the access transistors 5 and 6 are turned off (by applying a low voltage on row line 4). The SRAM cell 1 maintains its new logic state in a manner analogous to that described above.
FIGS. 2A and 2B are a schematic diagram and cross-section, respectively, of one of the CMOS inverters of FIG. 1 illustrating parasitic transistors and resistors of the inverter. As shown in FIG. 2B, the pull-down transistor 9 is formed within a P-type substrate 12 while the pull-up transistor 7 is formed within an N-well 14. The N-well 14 is formed within the P-type substrate 12. The N-well 14 includes parasitic resistance denoted by the resistor 16 and the P-type substrate includes parasitic resistance denoted by the resistor 18. The configuration of the pull-down transistor 9 and the pull-up transistor 7 results in the existence of a PNP parasitic bipolar transistor 20 and an NPN parasitic bipolar transistor 22.
With the tight layout spacings that exist in a typical memory array, leakage currents from the N-well 14 and the P-type substrate 12 are possible. These leakage currents produce a voltage drop across the parasitic resistor 16. If the voltage drop becomes sufficiently large, it can result in the parasitic PNP transistor 20 turning on and conducting current from the P+region forming its emitter to the P-type substrate 12 that forms its collector. The P-type substrate 12 also forms the base terminal of the parasitic NPN transistor 22 and one terminal of the parasitic resistor 18. The other terminal of the parasitic resistor 18 is the substrate tie-down represented by VBB. The current flowing through the resistor 18 produces a voltage rise at the point of injection. If this voltage rise becomes sufficiently large, it can result in the NPN transistor 22 turning on causing additional current to be drawn out the N-well 14 as collector current for the NPN transistor 22. This additional current reinforces the original leakage from the N-well 14 turning the PNP transistor 20 on even harder providing added base current for the NPN transistor 22. This feedback loop can result in a latch-up problem within the memory array containing the SRAM cell.
Accordingly, there is a need for an improved SRAM memory cell that is not prone to latch-up.